1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a merged memory-logic semiconductor device in which a memory and a logic circuit are implemented on a single semiconductor device.
2. Description of the Related Art
Referring to FIGS. 1A and 1B, a conventional merged memory-logic semiconductor device 101 includes a memory 111, a logic circuit 121 and a built-in self test (BIST) circuit 131. The memory 111 includes a plurality of memory cells (not shown). The BIST circuit 131 is used to test whether the plurality of memory cells operate normally. The logic circuit 121 stores data in the memory 111 or reads data stored in the memory 111 to perform a certain function. The memory 111 is electrically connected to the logic circuit 121 and the BIST circuit 131 via respective data buses 141 and 143. The memories 111 shown in FIGS. IA and IB have the same memory capacity, for example, 4 megabits.
Referring to FIG. 1A, each of the data buses 141 and 143 are four bits wide. In other words, 4 bits of data are input in parallel into the memory 111 from the logic circuit 121 or the BIST circuit 131, and, also, four bits of data are output in parallel from the memory 111 to the logic circuit 121 or the BIST circuit 131. Referring to FIG. 1B, data buses 151 and 153 are each eight bits wide. In other words, eight bits of data are input in parallel into the memory 111 from the logic circuit 121 or the BIST circuit 131, and, also, eight bits of data are output in parallel from the memory 111 to the logic circuit 121 or the BIST circuit 131. The sizes of the data buses 151 and 153 are determined based on user requirements.
As described above, in the conventional merged memory-logic semiconductor devices 101, the sizes of the data buses 141, 143, 151 and 153 connecting the respective memories 111 to the respective logic circuits 121 and to the respective BIST circuits 131, are determined based on user requirements, although the memories 111 have the same capacity. For this reason, not only is it expensive to develop the merged memory-logic semiconductor device 101, but it also takes longer for the BIST circuit 131 to test the memory 111 as the width of the data buses 141, 143, 151 and 153 becomes smaller.